The present invention is in the field of data processing and, in particular, relates to systems for improving the transfer of data between processors (or other input/output devices) and memory or data storage devices.
High speed computer systems employ memory devices to store data generated or modified by a processing unit or the like. The transfer of data to the memory is typically referred to as a "write instruction" or a "write." In most computer systems, the memory bus, across which data is transferred, is the same width as the buses employed by the processor to manipulate or generate data. Typically, processors operate on 16-bit or 32-bit strings of data values.
When a processor sends successive write instructions to memory, performance is compromised because the time required to transfer data is much greater than the processor's internal data manipulation cycle time. The processor must wait until each write instruction has been performed before continuing operations.
The conventional method for reducing performance costs during the transfer of data from a processor to memory has been to employ a first-in, first-out (FIFO) buffer, also known as a "write buffer," to store write instructions until the buffer is full or a break in processing operations occurs, at which time the buffer entries are unloaded serially into the memory. However, the value of a write buffer is dependent upon its depth as well as type of operations being performed by processor. Each write instruction will fill a separate location in the buffer and must be unloaded individually. A series of write instructions can quickly fill even a large write buffer.
Additionally, a problem can arise in the use of a write buffer when other operations, such as "read instructions" or "reads," are performed. A read instruction is a request to transfer data from memory to the processor. In order to avoid the possibility of a processor operating on stale data, in conventional systems all pending write instructions in the write buffer must be loaded into memory before a read instruction can be executed. The problem posed by the delay of read instructions while all pending write instructions are executed is often referred to as the "read latency" problem.
There exists a need for data transfer control systems which provide a way to transfer data to memory in quantities greater than the limits imposed by the width of the processor's data paths, e.g., greater than 16 bit or 32 bit operations. Such a system should allow the processor to continue operations with fewer interruptions for data transfer. Moreover, a system that alleviates or reduces the read latency problem associated with the execution of read requests when a write buffer is employed, would represent an advance in the field. A system having the above characteristics would be a substantial improvement over prior art techniques and would satisfy a long-felt need in the industry.